1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly to a method for fabricating a bowl-shaped capacitor for a dynamic random access memory (DRAM).
2. Description of the Prior Art
Please refer to FIGS. 1A through 1F, wherein the cross-sectional views of a conventional method for fabricating a DRAM cell are depicted in sequence.
Referring to FIG. 1A, a P-type semiconductor substrate 10 having a shallow trench isolation STI and transistors comprising gates G1, G2, G3 and N-type source and drain regions 12a, 12b, 12c is shown, wherein the gates G1, G2, G3 comprise an oxide layer 15, a polosilicon layer 16, a tungsten silicide layer 18, a silicon nitride masking layer 20, and a silicon nitride spacer 14.
Referring to FIG. 1B, a first insulating layer 24, for example, an oxide layer is formed on the semiconductor substrate 10. Subsequently, a first opening 26 for exposing the drain region 12b is formed by etching the first insulating layer 24. As shown in FIG. 1C, a bit line BL comprising a polysilicon layer 32 and a tungsten silicide layer 33 is then formed in the first opening 26.
Please refer to FIG. 1D. A second insulating layer 34, such as an oxide layer is globally formed on the first insulating layer 24. Subsequently, a second opening 35 for exposing the source region 12c is formed by etching the second and the first insulating layers 34 and 24.
Referring to FIG.1E, a conventional stacked capacitor is then formed by the following steps: forming a contact 51 in the second opening 35; forming a bottom electrode (conducting plate) 50 on the contact 51; forming a dielectric layer 52 on the bottom electrode 50; and forming an upper electrode (conducting plate) 54 on the dielectric layer 52. As well known by those persons skilled in this field, the most important parameters effecting the charges stored in the capacitor are the area of the capacitor plates, the dielectric constant, and the thickness of the insulator. Therefore, many approaches have been developed to increase the area of the electrodes by using different structures for the stacked capacitors to. For example, a crown capacitor is described in the U.S. Pat. No. 5,891,768, and a branch capacitor recited in the U.S. Pat. No. 5,904,522. However, the processes mentioned above are complicated, as etching and depositing steps must be very precise. Thus, the complexity and the cost of the processes are increased.